DATA SHEET
MOS INTEGRATED CIRCUIT
µPD75P308
4-BIT SINGLE-CHIP MICROCOMPUTER
DESCRIPTION
The µPD75P308 is a model of the µPD75308 equipped with a one-time PROM or EPROM instead of an
internal mask ROM.
Two types are available as the µPD75P308. The one-time PROM type is ideal for production of a small
quantity of many different types of application systems as data can only be written once to the one-time
PROM of this type. Programs can be written and rewritten to the built-in EPROM type making it ideal
for system evaluation.
Detailed functions are described in the followig user's manual. Be sure to read it for designing.
µPD75308 User's Manual: IEM-5016
FEATURES
• µPD75308 compatible
• Memory capacity
• Program memory (PROM): 8064 x 8 bits
• Data memory (RAM): 512 x 4 bits
• Can be connected to a pull-up resistor through software: Ports 0-3, 6, 7
• Open-drain input/output: Ports 4 and 5
• Single power source: 5V ± 5%
ORDERING INFORMATION
Part Number
Package
Internal ROM
µPD75P308GF-3B9
µPD75P308K
80-pin plastic QFP (14 x 20 mm)
One-time PROM
EPROM
80-pin ceramic WQFN (LCC w/window)
★
QUALITY GRADE
Part Number
Package
Quality Grade
µPD75P308GF-001-3B9
µPD75P308K
80-pin plastic QFP (14 x 20 mm)
Standard
Standard
80-pin Ceramic WQFN (LCC w/window)
Please refer to "Quality Grade on NEC Semiconductor Devices" (Document number IEI-1209) published by NEC
Corporation to know the specification of quality grade on the devices and its recommended applications.
The function common to the one-time PROM and EPROM types of product is referred to as PROM throughout this document.
The information in this document is subject to change without notice.
Document No. IC-2472B
(O. D. No. IC-7208C)
Date Published November 1993 P
Printed in Japan
The mark ★ shows major revised points.
NEC Corporation 1989
BASIC
4
4
4
4
4
4
4
4
PORT0
P00-P03
P10-P13
P20-P23
INTERVAL
TIMER
PORT1
PORT2
INTBT
PROGRAM
SP(8)
COUNTER(13)
CY
ALU
TI0/P13
TIMER/EVENT
COUNTER
#0
PTO0/P20
BANK
P30-P33
/MD0-MD3
INTT0
PORT3
PORT4
WATCH
TIMER
P40-P43
P50-P53
BUZ/P23
PROGRAM
MEMORY
(PROM)
PORT5
PORT6
PORT7
GENERAL REG.
fLCD
INTW
P60-P63
P70-P73
DECODE
AND
SI/SBI/P03
SO/SB0/P02
SCK/P01
SERIAL
DATA
MEMORY
(RAM)
INTERFACE
CONTROL
8064 x 8 BITS
INTCSI
512 x 4 BITS
24
8
S0-S23
INT0/P10
S24/BP0
-S31/BP7
INT1/P11
INT2/P12
INT4/P00
INTERRUPT
CONTROL
LCD
COM0-COM3
VLCO -VLC2
4
3
CONTROLLER
/DRIVER
8
KR0/P60-
KR3/P63,
KR4/P70-
KR7/P73
N
fX/2
SYSTEM CLOCK
GENERATOR
CLOCK
µ
CPU
STAND BY
CONTROL
CLOCK
DIVIDER
fLCD
OUTPUT
BIT SEQ.
BUFFER(16)
CLOCK
BIAS
CONTROL
MAIN
SUB
LCDCL/P30
SYNC/P30
PCL/P22
VSS
RESET
VPP VDD
X2
XT2 X1
XT1
µPD75P308
CONTENTS
1. PIN FUNCTIONS ................................................................................................................................. 5
1.1
1.2
1.3
1.4
PORT PINS ................................................................................................................................................. 5
NON PORT PINS ....................................................................................................................................... 6
PIN INPUT/OUTPUT CIRCUITS ................................................................................................................ 7
NOTES ON USING P00/INT4 AND RESET PINS..................................................................................... 9
★
2. DIFFERENCES BETWEEN µPD75P308 AND µPD75308.................................................................. 10
3. WRITING AND VERIFYING PROM (PROGRAM MEMORY) ........................................................... 11
3.1
3.2
3.3
3.4
OPERATION MODES FOR WRITING/VERIFYING PROGRAM MEMORY ............................................ 11
PROGRAM MEMORY WRITE PROCEDURE .......................................................................................... 12
PROGRAM MEMORY READ PROCEDURE ............................................................................................ 13
ERASURE (µPD75P308K ONLY) ............................................................................................................. 14
4. ELECTRICAL SPECIFICATIONS........................................................................................................ 15
5. PACKAGE DRAWINGS ......................................................................................................................28
6. RECOMMENDED SOLDERING CONDITIONS................................................................................. 30
APPENDIX A. DEVELOPMENT TOOLS ................................................................................................. 31
APPENDIX B. RELATED DOCUMENTS ................................................................................................ 32
★
4
µPD75P308
1. PIN FUNCTIONS
1.1 PORT PINS
Input/
Output
Also Served
As
Pin Name Input/Output
Function
8-Bit I/O
X
When Reset
Circuit
TYPE*1
B
P00
P01
P02
P03
P10
P11
P12
P13
Input
INT4
SCK
4-bit input port (PORT0)
Pull-up resistors can be specified in 3-bit
units for the P01 to P03 pins by software.
Input/Output
Input/Output
Input/Output
F -A
F -B
M -C
Input
Input
SO/SB0
SI/SBI
INT0
INT1
INT2
TI0
With noise elimination function
4-bit input port (PORT1)
Internal pull-up resistors can be
specified in 4-bit units by software.
X
B -C
E-B
E-B
Input
P20
P21
PTO0
—
4-bit input/output port (PORT2)
Internal pull-up resistors can be
specified in 4-bit units by software.
Input/Output
X
X
Input
Input
P22
P23
PCL
BUZ
Programmable 4-bit input/output port
(PORT3)
P30*2
P31*2
P32*2
P33*2
LCDCL MD0
SYNC
MD1
This port can be specified for input/output
in bit units.
Input/Output
MD2
Internal pull-up resistors can be
specified in 4-bit units by software.
MD3
N-ch open-drain 4-bit input/output port
(PORT4)
P40-43*2 Input/Output
—
Data input/output pin for writing and
verifying of program memory (PROM)
(lower 4 bits)
High impedance
High impedance
M-A
M-A
●
N-ch open-drain 4-bit input/output port
(PORT5)
P50-P53*2 Input/Output
P60
—
Data input/output pin for writing and
verifying of program memory (PROM)
(upper 4 bits)
KR0
KR1
KR2
KR3
KR4
KR5
KR6
KR7
S24
S25
S26
S27
S28
S29
S30
S31
Programmable 4-bit input/output port
(PORT6)
P61
This port can be specified for input/output
in bit units.
Input/Output
P62
Input
Input
F -A
F -A
Internal pull-up resistors can be specified
in 4-bit units by software.
P63
P70
●
4-bit input/output port (PORT7)
Internal pull-up resistors can be
specified in 4-bit units by software.
P71
Input/Output
P72
P73
BP0
BP1
Output
BP2
BP3
BP4
BP5
1-bit output port (BIT PORT)
Shared with a segment output pin.
G-C
X
★
*3
Output
BP6
BP7
*1: Circles indicate schmitt trigger inputs.
2: Can directly drive LED.
3: For BP0-7, VLC1 indicated below are selected as the input source.
However, the output level is changed depending on BP0-7 and the VLC1 external circuits.
5
µPD75P308
1.2 NON PORT PINS
Input/
Output
Circuit
TYPE*1
Also Served
As
Pin Name Input/Output
Function
When Reset
Timer/event counter external event pulse input
Timer/event counter output
Clock output
B -C
TI0
PTO0
PCL
Input
Output
P13
P20
P22
—
E-B
Input
Input
Input/Output
E-B
Fixed frequency output (for buzzer or for trimming
the system clock)
BUZ
SCK
Input/Output
Input/Output
P23
P01
P02
Input
E-B
F -A
F -B
Serial clock input/output
Input
Input
Serial data output
SO/SB0 Input/Output
SI/SB1 Input/Output
Serial bus input/output
Serial data input
P03
P00
Input
—
M -C
Serial bus input/output
Edge detection vector interrupt input (either rising
or falling edge detection is effective)
INT4
Input
B
Edge detection vector interrupt input (detection
edge can be selected)
INT0
INT1
INT2
P10
P11
—
B -C
Input
Input
B -C
F -A
F -A
G-A
Edge detection testable input (rising edge detection)
Testable input/output(parallel falling edge detection)
Testable input/output(parallel falling edge detection)
Segment signal output
—
Input
Input
*3
P12
KR0-KR3 Input/Output
KR4-KR7 Input/Output
P60-P63
P70-P73
—
S0-S23
Output
Output
G-C
★
Segment signal output
*3
S24-S31
BP0-7
COM0-
COM3
Common signal output
LCD drive power
*3
G-B
—
Output
—
VLC0-VLC2
—
—
—
—
—
High-impedance
Input
BIAS
—
External dividing resistor disconnect output
Externally expanded driver clock output
Externally expanded driver sync clock output
LCDCL*2 Input/Output
SYNC*2 Input/Output
P30
P31
E-B
E-B
Input
To connect the crystal/ceramic oscillator to the main
system clock generator.
X1, X2
XT1
Input
Input
—
—
—
—
—
When inputting the external clock, input the external
clock to pin X1, and the reverse phase of the
external clock to pin X2.
To connect the crystal oscillator to the subsystem
clock generator.
—
—
When the external clock is used, in XT1 inputs the
external clock. In this case, pin XT2 must be left
open.
XT2
—
Pin XT1 can be used as a 1-bit input (test) pin.
B
RESET
Input
—
System reset input (low level active)
—
To select mode when writing/verifying of program
memory (PROM)
Input
MD0-MD3 Input/Output
P30-P33
E-B
Program voltage application when writing and
verifying of program memory (PROM)
Connect to VDD during the normal operation
VPP
—
—
—
—
Apply +12.5V when writing/verifying EPROM
Positive power supply
—
—
VDD
—
—
—
—
—
—
VSS
GND
*1: Circles indicate schmitt trigger inputs.
2: These pins are provided for future system expansion. At present, these pins are used only as pins P30 and P31.
3: For these display output, VLCX indicated below are selected as the input source.
S0 to S31: VLC1, COM0 to COM2: VLC2, COM3: VLC0
However, display output level varies depending on the particular display output and VLCX external circuit.
6
µPD75P308
1.3 PIN INPUT/OUTPUT CIRCUITS
The following shows a simplified input/output circuit diagram for each pin of the µPD75P308.
TYPE A (for TYPE E–B)
TYPE D (for TYPE E–B, F-A)
VDD
data
P–ch
N–ch
P–ch
N–ch
OUT
IN
output
disable
Push–pull output that can be set in a output
high–impedance state (both P–ch and N–ch are off)
Input buffer of CMOS standard
TYPE B
TYPE E–B
VDD
P.U.R.
P.U.R.
P–ch
enable
IN
data
IN/OUT
Type D
output
disable
Type A
Schmitt trigger input with hysteresis characteristics
TYPE B–C
P.U.R. : Pull–Up Resistor
VDD
TYPE E–E
P.U.R.
VDD
P.U.R.
P–ch
enable
P.U.R.
data
P.U.R.
enable
IN/OUT
Type D
P–ch
output
disable
IN
Type A
Type B
P.U.R. : Pull
–Up Resistor
Schmitt trigger input with hysteresis characteristics
P.U.R. : Pull–Up Resistor
7
µPD75P308
TYPE G–B
TYPE F–A
VDD
VLC0
P-ch
P.U.R.
enable
P–ch
VLC1
data
P-ch N-ch
N-ch P-ch
IN/OUT
Type D
output
disable
OUT
COM
data
Type B
VLC2
P.U.R. : Pull–Up Resistor
N-ch
TYPE F–B
TYPE G–C
VDD
P.U.R.
VDD
P-ch
P.U.R.
enable
P–ch
output
VLC0
VDD
disable
(P)
VLC1
P-ch
IN/OUT
P-ch
OUT
N-ch
data
output
disable
SEG
data/Bit Port data
N-ch
output
disable
(N)
VLC2
N-ch
P.U.R. : Pull–Up Resistor
TYPE G–A
TYPE M–A
VLC0
IN/OUT
P-ch
data
VLC1
N-ch
P-ch
output
disable
SEG
data
OUT
N-ch
VLC2
N-ch
Middle voltage input buffer
8
µPD75P308
TYPE M-C
VDD
P.U.R.
P.U.R.
enable
P–ch
IN/OUT
data
N-ch
output
disable
P.U.R. : Pull–Up Resistor
1.4 NOTES ON USING P00/INT4 AND RESET PINS
In addition to the functions shown in sections 1.1 and 1.2, the P00/INT4 and RESET pins also have a function
to set a test mode (for IC testing) in which the internal operations of the µPD75P308 are tested.
When a voltage higher than VDD is applied to either of these pins, the test mode is set. This means that, even
during ordinary operation, the µPD75P308 may be set in the test mode if a noise exceeding VDD is applied.
For example, if the wiring length of the P00/INT4 or RESET pin is too long, noise superimposed on the wiring
line of the pin may cause the above problem.
Therefore, keep the wiring length of these pins as short as possible to suppress the noise; otherwise, take noise
preventive measures as shown below by using external components.
•
Connect capacitor between VDD
and P00/INT4, RESET pin
•
Connect diode with low VF between VDD
and P00/INT4, RESET pin
V
DD
V
DD
Diode with
low VF
V
DD
V
DD
P00/INT4, RESET
P00/INT4, RESET
9
µPD75P308
2. DIFFERENCES BETWEEN µPD75P308 AND µPD75308
The µPD75P308 is a model of the µPD75308 and is equipped with a PROM instead of a mask ROM.
Programs can be rewritten to the PROM of the µPD75P308. Table 2-1 shows the differences between the
µPD75P308 and µPD75308. You should fully consider these differences when you debug or produce your
application system on an experimental basis by using the PROM model, and then proceed to mass-produce
the system by using the mask ROM model.
For the details of the CPU and the internal hardware, refer to µPD75308 User's Manual (IEM-5016).
Table 2-1 Differences between µPD75P308 and µPD75308
Item
µPD75P308K
• EPROM
µPD75P308GF
µPD75308GF
• Mask ROM
• PROM (one-time model)
• 0000H-1F7FH
• 0000H-1F7FH
• 8064 x 8 bits
• 0000H-1F7FH
• 8064 x 8 bits
Program Memory
• 8064 x 8 bits
Pull-up Resistor
Ports 4, 5
Not provided
Mask option
Dividing Resistor for LCD
Driving Power Supply
Not provided
Mask option
Pins 50-53
P30/MD0-P33/MD3
VPP
P30-P33
NC
Pin Connection
Pin 57
Current dissipations and operating temperature ranges differ between µPD75P308 and
Electrical Specifications
µPD75308. For detail, refer to the specification documents of each mode.
★
Operating Voltage Range
Package
5V±5%
2.7-6.0V
80-pin ceramic WQFN
(LCC w/window)
80-pin plastic QFP (14 x 20 mm)
Noise immunity and noise radiation differ because circuit scale and mask layout are
different.
Others
★
★
Note: The noise immunity and noise radiation differ between the PROM and mask ROM models. To replace
the PROM model with the mask ROM model in the course of experimental production to mass
production, evaluate your system by using the CS mode (not ES model) of the mask ROM model.
10
µPD75P308
3. WRITING AND VERIFYING PROM (PROGRAM MEMORY)
The program memory of the µPD75P308 is a PROM of 8064 x 8 bits. To write data to or verify the contents
of this PROM, the pins listed in the table below are used. Note that no address input pins are provided
because the address is updated by the clock input through the X1 pin.
Pin Name
Function
VPP
Applies voltage when program memory is written/verified (normally, at VDD potential)
These pins input clock that updates address when program memory is written/verified. To X2 pin,
input signal 180º out of phase in respect to signal to X1 pin.
X1, X2
MD0-MD3
These pins select operation mode when program memory is written/verified.
These pins input/output 8-bit data when program memory is written/verified.
P40-P43 (Lower 4)
P50-P53 (Upper 4)
Power supply voltage application pin.
VDD
Apply 5V ± 5% to this pin during normal operation and 6V when program memory is written/verified.
Note 1: Always cover the erasure window of the µPD75P308K with a light-opaque film except when the
contents of the program memory are erased.
2: The one-time PROM model µPD75P308GF is not equipped with a window and therefore, the
contents of the program memory of this model cannot be erased by exposing it to ultraviolet rays.
3.1 OPERATION MODES FOR WRITING/VERIFYING PROGRAM MEMORY
When +6V is applied to the VDD pin of the µPD75P308 with +12.5V applied to the VPP pin, the µPD75P308
is set in the program memory write/verify mode. In this mode, the following operation modes can be set
by using the MD0-MD3 pins. At this time, pull down the levels of all the other pins to VSS.
Operating Mode Specification
Operating Mode
VPP
VDD
MD0
MD1
MD2
MD3
H
L
L
H
L
H
L
Program memory address 0 clear mode
Write mode
H
H
+12.5 V
+6 V
L
H
H
Verify mode
H
x
H
H
Program inhibit mode
x: L or H
11
µPD75P308
3.2 PROGRAM MEMORY WRITE PROCEDURE
The program memory write procedure is as follows. High-speed program memory write is possible.
(1) Ground the unused pins through pull-down resistors. The X1 pin must be low.
(2) Supply 5 V to the VDD and VPP pins.
(3) Wait for 10 microseconds.
(4) Set program memory address 0 clear mode.
(5) Supply 6 V to the VDD pin and 12.5 V to the VPP pin.
(6) Set program inhibit mode.
(7) Write data in 1-millisecond write mode.
(8) Set program inhibit mode.
(9) Set verify mode. If data has been written connectly, proceed to step (10). If data has not yet been
written, repeat steps (7) to (9).
(10) Write additional data for (the number of times data was written (X) in steps (7) to (9)) times
1 milliseconds.
(11) Set program inhibit mode.
(12) Supply a pulse to the X1 pin four times to update the program memory address by 1.
(13) Repeat steps (7) to (12) to the last address.
(14) Set program memory address 0 clear mode.
(15) Change the voltages of VDD and VPP pins to 5 V.
(16) Turn off the power supply.
Steps (2) to (12) are illustrated below.
X-time repetition
Additional
data write
Address
increment
Write
Verify
VPP
VPP
VDD
VDD+1
VDD
VDD
X1
P40-P43
P50-P53
Data
output
Data input
Data input
MD0
(P30)
MD1
(P31)
MD2
(P32)
MD3
(P33)
12
µPD75P308
3.3 PROGRAM MEMORY READ PROCEDURE
The contents of the program memory can be read in the following procedure.
(1) Ground the unused pins through pull-down resistors. The X1 pin must be low.
(2) Supply 5 V to the VDD and VPP pins.
(3) Wait for 10 microseconds.
(4) Set program memory address 0 clear mode.
(5) Supply 6 V to the VDD pin and 12.5 V to the VPP pin.
(6) Set program inhibit mode.
(7) Set verify mode. Data of each address is sequentially output each time a clock pulse is input to the
X1 pin four times.
(8) Set program inhibit mode.
(9) Set program memory address 0 clear mode.
(10) Change the voltages of VDD and VPP pins to 5 V.
(11) Turn off the power supply.
Steps (2) to (9) are illustrated below.
VPP
VPP
VDD
VDD+1
VDD
VDD
X1
P40-P43
P50-P53
Data output
Data output
MD0
(P30)
MD1
(P31)
MD2
(P32)
MD3
(P33)
13
µPD75P308
3.4 ERASURE (µPD75P308K ONLY)
The contents of the data programmed to the µPD75P308 can be erased by exposing the window of the
program memory to ultraviolet rays.
The wavelength of the ultraviolet rays used to erase the contents is about 250 nm, and the quantity of the
ultraviolet rays necessary for complete erasure is 15 W.s/cm2 (= ultraviolet ray intensity x erasure time).
When a commercially available ultraviolet ray lamp (wavelength: 254 nm, intensity: 12 mW/cm2) is used,
about 15 to 20 minutes is required.
Note 1: The contents of the program memory may be erased when the µPD75P308 is exposed for a long
time to direct sunlight or the light of fluorescent lamps. To protect the contents from being
erased, mask the window of the program memory with the light-opaque film supplied as an
accessory with the UV EPROM products.
2: To erase the memory contents, the distance between the ultraviolet ray lamp and theµPD75P308
should be 2.5 cm or less.
Remarks:
The time required for erasure changes depending on the degradation of the ultraviolet ray
lamp and the surface condition (dirt) of the window of the program memory.
14
µPD75P308
4. ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS (Ta = 25°C)
Parameter
Supply Voltage
Supply Voltage
Symbol
VDD
Conditions
Rating
Unit
V
-0.3 to +7.0
VPP
-0.3 to +13.5
V
VI1
Other than ports 4 or 5
-0.3 to VDD+0.3
V
Input Voltage
*1
VI2
Ports 4 and 5
Open-drain
-0.3 to +11
V
Output Voltage
VO
-0.3 to VDD+0.3
V
1 Pin
-15
mA
mA
mA
mA
mA
mA
mA
mA
°C
High-Level Output Current
IOH
All pins
-30
Peak value
30
15
One pin
Effective value
Peak value
100
*2
Low-Level Output Current
Total of ports 0, 2, 3, 5
Total of ports 4, 6, 7
IOH
Effective value
Peak value
60
100
Effective value
60
Operating Temperature
Storage Temperature
Topt
Tstg
-10 to +70
-65 to +150
°C
*1:
2:
The impedance of the power source (pull-up resistor) must be 50 KΩ minimum when a voltage higher
than 10V is applied to ports 4 and 5.
Effective value = Peak value x √Duty
15
µPD75P308
MAIN SYSTEM CLOCK OSCILLATOR CIRCUIT CHARACTERISTICS
(Ta = -10 to +70°C, VDD = 5 to ±5 V)
Recommended
Oscillator
Ceramic*3
Item
Conditions
MIN.
1.0
TYP. MAX.
Unit
MHz
ms
Constants
Oscillation
frequency (fXX)*1
Oscillation stabilization After VDD came to MIN.
5.0*4
4
X1 X2
C1
C1
C2
C2
time*2
of oscillation voltage range
VDD
X2
Crystal
Oscilaltion
1.0
4.19
5.0*4
10
MHz
ms
X1
X1
frequency (fXX)*1
Oscillation stabilization
time*2
VDD
X2
External Clock
X1 input frequency
(fX)*1
1.0
5.0*4
500
MHz
ns
X1 input high-, low-level
widths (tXH, tXL)
100
µ
PD74HCU04
*1: The oscillation frequency and X1 input frequency are indicated only to express the characteristics of the
oscillator circuit.
For instruction execution time, refer to AC Characteristics.
2: Time required for oscillation to stabilize after VDD reaches the minimum value of the oscillation voltage
range or the STOP mode has been released.
3: The oscillators below are recommended.
★
★
4: When the oscillation frequency is 4.19 MHz < fx ≤ 5.0 MHz, do not select PCC = 0011 as the instruction
execution time: otherwise, one machine cycle is set to less than 0.95 µs, falling short of the rated
minimum value of 0.95 µs.
Caution: When using the oscillation circuit of the main system clock, wire the portion enclosed in dotted
line in the figures as follows to avoid adverse influences on the wiring capacity:
•
•
Keep the wiring length as short as possible.
Do not cross the wiring over the other signal lines. Do not route the wiring in the vicinity of
lines through which a high alternating current flows.
•
•
Always keep the ground point of the capacitor of the oscillator circuit at the same potential
as VDD. Do not connect the power source pattern through which a high current flows.
Do not extract signals from the oscillation circuit.
RECOMMENDED OSCILLATION CIRCUIT CONSTANTS
MAIN SYSTEM CLOCK: CERAMIC OSCILLATOR (Ta = -10 to +70°C)
Oscillation
Voltage Range [V]
External Capacitance [pF]
Manufac-
turer
Product Name
C1
C2
MIN.
4.75
4.75
4.75
4.75
MAX.
5.25
5.25
5.25
5.25
Murata
Mfg.
Co., Ltd.
CSA 2.00MG
CSA 4.19MG
CSA 4.19MGU
CST 4.19MG
30
30
30
30
30
30
30 pF (internal)
30 pF (internal)
16
µPD75P308
SUBSYSTEM CLOCK OSCILLATOR CIRCUIT CHARACTERISTICS
(Ta = -10 to +70°C, VDD = 5 V ±5%)
Recommended
Oscillator
Crystal
Item
Oscillation
Conditions
MIN.
32
TYP. MAX.
Unit
kHz
Constants
XT1
XT2
32.768
1.0
35
frequency (fXT)
R
Oscillation stabilization
time*
C3
C4
2
s
VDD
External Clock
XT1 input frequency
(fXT)
32
5
100
15
kHz
µs
XT1
XT2
Open
XT1 input high-, low-level
widths (tXTH, tXTL)
*: Time required for oscillation to stabilize after VDD reaches the minimum value of the oscillation voltage
range.
Caution: When using the oscillation circuit of the subsystem clock, wire the portion enclosed in dotted line
in the figures as follows to avoid adverse influences on the wiring capacity:
★
•
•
Keep the wiring length as short as possible.
Do not cross the wiring over the other signal lines. Do not route the wiring in the vicinity of
lines through which a high alternating current flows.
•
•
Always keep the ground point of the capacitor of the oscillator circuit at the same potential
as VDD. Do not connect the power source pattern through which a high current flows.
Do not extract signals from the oscillation circuit.
The amplification factor of the subsystem clock oscillation circuit is designed to be low to reduce the
current dissipation and therefore, the subsystem clock oscillation circuit is influenced by noise more
easily than the main system clock oscillation circuit. When using the subsystem clock, therefore,
exercise utmost care in wiring the circuit.
CAPACITANCE (Ta = 25°C, VDD = 0 V)
Parameter
Input Capacitance
Output Capacitance
Symbol
Conditions
MIN.
TYP. MAX. Unit
CIN
f = 1 MHz
Pins other than thosemeasured are at 0 V
15
15
pF
pF
COUT
CIO
Input/Output
Capacitance
15
pF
17
µPD75P308
DC CHARACTERISTICS (Ta = -10 to +70°C, VDD = 5V ±5%)
Parameter
Symbol
Conditions
MIN. TYP. MAX. Unit
Ports 2, 3
Ports 0, 1, 6, 7, RESET
High-Level Input Voltage
0.7 VDD
0.8 VDD
0.7 VDD
VDD-0.5
0
VDD
VDD
V
V
V
V
V
V
V
VIH1
VIH2
VIH3
VIH4
VIL1
VIL2
VIL3
Ports 4, 5
Open-drain
10
X1, X2, XT1
VDD
Ports 2, 3, 4, 5
Ports 0, 1, 6, 7, RESET
X1, X2, XT1
Ports 0, 2, 3, IOH = -1mA
6, 7
Low-Level Input Voltage
High-Level Output Voltage
Low-Level Output Voltage
0.3 VDD
0.2 VDD
0.4
0
0
VDD-1.0
V
VOH1
VOH2
VOL1
BIAS
BP0-7
IOH = -100µA*1
VDD-2.0
V
V
Ports 0, 2, 3, Ports 3, 4, 5
0.4
2.0
6, 7
IOL = 15mA
IOL = 1.6mA
0.4
V
V
SB0, 1
Open-drain
VOL2
0.2VDD
Pull-up R ≥ 1kΩ
VOL3
ILIH1
ILIH2
ILIH3
ILIL1
BP0-7
IOL = 100µA*1
Other than below
X1, X2, XT1
1.0
3
V
High-Level Input Leakage Current
µA
µA
µA
µA
µA
µA
µA
µA
VIN = VDD
20
20
-3
VIN = 10V
VIN = 0V
Ports 4, 5
Low-Level Input Leakage Current
High-Level Output Leakage Current
Other than below
X1, X2, XT1
ILIL2
-20
3
ILOH1
ILOH2
ILOL
VOUT = VDD
VOUT = 10V
VOUT = 0V
Other than below
Ports 4.5
20
-3
Low-Level Output Leakage Current
Internal Pull-Up Resistor
Ports 0, 1, 2, 3, 6, 7
(except P00) VIN = 0V
RLI
15
40
80
KΩ
VLCD
LCD Drive Voltage
2.5
VDD
V
2
2
3
*
VLCD0 = VLCD
LCD Output Voltage Deviation
(Common)
I0 = ±5 µA
VODC
VODS
0
0
±0.2V
V
V
2
VLCD1 = VLCD x —
3
1
*
*
VLCD2 = VLCD x —
LCD Output Voltage Deviation
(Segment)
2.7 V ≤ VLCD ≤ 3VDD
±0.2V
I0 = ±1 µA
4.19MHz crystal *4
oscillator
6
*
Supply Current
IDD1
IDD2
5
15
mA
HALT mode
HALT mode
500
350
35
1500
1000
100
µA
C1 = C2 = 22pF
5
32 kHz
*
IDD3
IDD4
µA
crystal oscillator
XT1 = 0V
0.5
20
µA
STOP mode
* 1: When using two of BP0-BP3 and two of BP4-BP7 for output at the same time.
2: "Voltage deviation" means the difference between the ideal segment or common output value
(VLCDn: = 0, 1, 2) and output voltage.
3: Currents for the built-in pull-up resistor are not included.
4: Including when the subsystem clock is operated.
5: When operated with the subsystem clock by setting the system clock control register (SCC) to
1001 to stop the main system clock operation.
6: When operand in the high-speed mode with the processor clock control register (PCC) set to 0011.
18
µPD75P308
AC CHARACTERISTICS (Ta = -10 to + 70°C, VDD = 5V ±5%)
Operation Other Than Serial Transfer
Parameter
CPU Clock Cycle Time*1
(Minimum Instruction
Execution Time
Symbol
Conditions
MIN.
0.95
TYP.
122
MAX.
64
Unit
w/main system clock
µs
tCY
w/subsystem clock
114
125
1
µs
= 1 Machine Cycle)
TI0 Input Frequency
TI0 Input High-, Low-Level
Widths
fTI
0
MHz
tTIH, tTIL
0.48
µs
tINTH,
tINTL
tRSL
InterruptInputHigh-,Low-Level
Widths
*2
10
10
µs
µs
µs
INT0
KR0-7, INT1, 2, 4
RESET Low-Level Width
t
cy vs VDD
(with main system clock)
70
* 1: The CPU clock (Φ) cycle time is determined
bytheoscillationfrequencyoftheconnected
oscillator, system clock control register
(SCC), and processor clock control register
(PCC).
64
60
6
5
The figure on the right is cycle time tCY vs.
supply voltage VDD characteristics at the
main system clock.
4
3
µ
2: 2tCY or 128/fXX depending on the setting of
the interrupt mode register (IM0).
2
1
0.5
0
1
2
3
4
5
6
DD
Supply voltage V [V]
19
µPD75P308
SERIAL TRANSFER OPERATION
TWO-LINE AND THREE-LINE SERIAL I/O MODES (SCK: internal clock output)
Parameter
SCK Cycle Time
SCK High-, Low-Level Widths
Symbol
Conditions
MIN.
1600
TYP.
MAX.
Unit
ns
Output
tKCY1
tKH1, tKL1
tSIK1
Output tKCY1/2-50
ns
↑
SI Set-Up Time (vs. SCK
)
150
400
ns
↑
ns
SI Hold Time (vs. SCK
)
tKSI1
↓ →
RL = 1kΩ, CL = 100pF*
250
ns
SCK
SO Output
tKSO1
Delay Time
★
*: RL and CL are load resistance and load capacitance of the SO output line.
TWO-LINE AND THREE-LINE SERIAL I/O MODES (SCK: external clock input)
Parameter
SCK Cycle Time
SCK High-, Low-Level Widths
Symbol
Conditions
MIN.
800
400
100
400
TYP.
MAX.
Unit
ns
Input
Input
tKCY2
tKH2, tKL2
tSIK2
ns
↑
SI Set-Up Time (vs. SCK
)
ns
↑
SI Hold Time (vs. SCK
)
ns
tKSI2
↓ →
RL = 1kΩ, CL = 100pF*
300
ns
SCK
SO Output
tKSO2
Delay Time
★
*: RL and CL are load resistance and load capacitance of the SO output line.
20
µPD75P308
SBI MODE (SCK: internal clock output (master))
Parameter
SCK Cycle Time
Symbol
Conditions
MIN.
1600
TYP.
MAX.
Unit
ns
tKCY3
tKL3
tKCY/2
SCK High-, Low-Level
Widths
ns
tKH3
tSIK3
tKSI3
-50
↑
SB0, 1 Set-Up Time (vs. SCK
)
)
150
ns
ns
↑
SB0, 1 Hold Time (vs. SCK
tKCY/2
↓ →
Delay Time
SCK
SB0, 1 Output
tKSO3
0
250
ns
RL = 1kΩ, CL = 100pF*
tKSB
tSBK
SCK↑ → SB0, 1↓
tKCY
tKCY
tKCY
tKCY
ns
ns
ns
ns
↓ →
↓
SCK
SB0, 1
SB0, 1 Low-Level Width
SB0, 1 High-Level Width
tSBL
tSBH
★
*: RL and CL are load resistance and load capacitance of the SO output line.
SBI MODE (SCK: external clock output (master))
Parameter
SCK Cycle Time
Symbol
Conditions
MIN.
1600
TYP.
MAX.
Unit
ns
tKCY4
tKL4
SCK High-, Low-Level
Widths
400
ns
tKH4
tSIK4
tKSI4
↑
SB0, 1 Set-Up Time (vs. SCK
)
)
100
tKCY/2
0
ns
ns
ns
↑
SB0, 1 Hold Time (vs. SCK
↓ →
SCK
Delay Time
↑ →
SB0, 1 Output
300
tKSO4
RL = 1kΩ, CL = 100pF*
tKSB
tSBK
SCK
SB0, 1
SB0, 1↓
↓ →
tKCY
tKCY
tKCY
tKCY
ns
ns
ns
ns
↓
SCK
SB0, 1 Low-Level Width
SB0, 1 High-Level Width
tSBL
tSBH
*: RL and CL are load resistance and load capacitance of the SO output line.
★
21
µPD75P308
AC TIMING TEST POINT (excluding X1 and XT1 inputs)
0.8 VDD
0.8 VDD
0.2 VDD
Test points
0.2 VDD
CLOCK TIMING
1/fX
tXL
tXH
X1 input
VDD –0.5V
0.4 V
1/fXT
tXTL
tXTH
XT1 input
VDD –0.5V
0.4 V
TI0 TIMING
1/fTI
tTIL
tTIH
TI0
22
µPD75P308
SERIAL TRANSFER TIMING
THREE-LINE SERIAL I/O MODE:
tKCY1
tKL1
tKH1
SCK
tSIK1
tKSI1
SI
Input data
tKSO1
Output data
SO
TWO-LINE SERIAL I/O MODE:
tKCY
tKH
tKL
SCK
tKSO
tSIK
tKSI
SB0,1
23
µPD75P308
SERIAL TRANSFER TIMING
BUS RELEASE SIGNAL TRANSFER
KCY3,4
t
tKL3,4
tKH3,4
SCK
tSIK3,4
tKSB
tSBL
tSBH
tSBK
tKSI3,4
SB0,1
tKSO3,4
COMMAND SIGNAL TRANSFER
tKCY3,4
tKL3,4
tKH3,4
SCK
tSIK3,4
tKSB
tSBK
tKSI3,4
SB0,1
tKSO3,4
INTERRUPT INPUT TIMING
tINTL
tINTH
INT0, 1, 2, 4
KR0-7
RESET INPUT TIMING
tRSL
RESET
24
µPD75P308
LOW-VOLTAGE DATA RETENTION CHARACTERISTICS OF DATA MEMORY IN STOP MODE
(Ta = -10 to +70°C)
Parameter
Symbol
Conditions
MIN.
2.0
TYP.
MAX.
6.0
Unit
V
Data Retention Supply
Voltage
VDDDR
Data Retention Supply
Current*1
IDDDR
VDDDR = 2.0V
0.1
10
µA
0
µs
tSREL
tWAIT
Release Signal Set Time
Oscillation Stabilization
Wait Time*2
217/fX
ms
ms
Released by RESET
3
*
Released by interrupt
*1: Does not include current folowing through internal pull-up resistor
2: The oscillation stabilization wait time is the time during which the CPU is stopped to prevent unstable
operation when oscillation is started.
3: Depends on the setting of the basic interval timer mode register (BTM) as follows:
BTM3
—
BTM2
BTM1
BTM0
—
WAIT time ( ): fX = 4.19 MHz
220/fX (approx. 250 ms)
217/fX (approx. 31.3 ms)
215/fX (approx. 7.82 ms)
213/fX (approx. 1.95 ms)
0
0
1
1
0
1
0
1
—
—
—
—
—
—
DATA RETENTION TIMING (releasing STOP mode by RESET)
Internal reset operation
HALT mode
STOP mode
Operation
mode
Data retention mode
VDD
VDDDR
tSREL
STOP instruction
execution
RESET
tWAIT
DATA RETENTION TIMING (standby release signal: releasing STOP mode by interrupt)
HALT mode
STOP mode
Data retention mode
Operation
mode
VDD
VDDDR
tSREL
STOP instruction execution
Standby release signal
(interrupt request)
tWAIT
25
µPD75P308
DC PROGRAMMING CHARACTERISTICS (Ta = 25 ±5°C, VDD = 6.0±0.25V, VPP = 12.5±0.3V, VSS = 0V)
Parameter
Symbol
Conditions
Other than X1 or X2
MIN.
0.7 VDD
VDD –0.5
0
TYP.
MAX.
VDD
Unit
V
VIH1
VIH2
VIL1
VIL2
ILI
High-Level Input Voltage
X1 and X2
VDD
V
Other than X1 or X2
X1 and X2
0.3 VDD
0.4
V
Low-Level Input Voltage
0
V
Input Leakage Current
High-Level Output Voltage
Low-Level Output Voltage
VDD Supply Current
VIN = VIL or VIH
IOH = –1 mA
10
µA
V
VDD –1.0
VOH
VOL
IDD
IOL = 1.6 mA
0.4
30
30
V
mA
mA
VPP Supply Current
MD0 = VIL, MD1 = VIH
IPP
Notes 1: VPP must not exceed +13.5 V, including the overshoot.
2: Apply VDD before VPP and disconnect it after VPP.
AC PROGRAMMING CHARACTERISTICS (Ta = 25±5°C, VDD = 6.0±0.25V, VPP = 12.5±0.3V, VSS = 0V)
1
Parameter
Symbol
*
Conditions
MIN. TYP. MAX. Unit
Address Set-Up Time*2 (vs.MD0↓)
MD1 Set-Up Time (vs. MD0↓)
Data Set-Up Time (vs. MD0↓)
Address Hold Time*2 (vs.MD0↑)
Data Hold Time (vs. MD0↑)
tAS
tM1S
tDS
tAS
tOES
tDS
tAH
tDH
tDF
tVPS
tVCS
tPW
tOPW
tCES
tDV
tOEH
tOR
–
2
2
µs
µs
µs
µs
µs
ns
µs
µs
ms
ms
µs
µs
µs
µs
µs
µs
2
2
tAH
2
tDH
0
130
MD0 ↑→ Data Output Float Delay Time
VPP Set-Up Time (vs. MD3↑)
VDD Set-Up Time (vs. MD3↑)
Initial Program Pulse Width
Additional Program Pulse Width
MD0 Set-Up Time (vs. MD1↑)
MD0 ↓→ Data Output Delay Time
MD1 Hold Time (vs. MD0↑)
tDF
2
tVPS
tVDS
tPW
2
0.95
0.95
2
1.0
1.05
21.0
tOPW
tMOS
tDV
1
MD0 = MD1 = VIL
2
2
tM1H
tM1R
tPCR
tXH,tXL
fX
tM1H + tM1R ≥ 50 µs
MD1 Recovery Time (vs. MD0↓)
Program Counter Reset Time
X1 Input High-/Low- Level Width
X1 Input Frequency
10
0.125
–
4.19 MHz
–
2
2
2
2
µs
µs
µs
µs
Initial Mode Set Time
tI
–
MD3 Set-Up Time (vs. MD1↑)
MD3 Hold Time (vs. MD1↓)
tM3S
tM3H
tM3SR
tDAD
tHAD
tM3HR
tDFR
–
–
When data is read from program memory
When data is read from program memory
When data is read from program memory
When data is read from program memory
When data is read from program memory
MD3 Set-Up Time (vs. MD0↓)
Address*2 → Data Output Delay Time
Address*2 → Data Output Hold Time
MD3 Hold Time (vs. MD0↑)
–
★
★
2
µs
ns
µs
µs
tACC
tOH
–
0
2
130
2
MD3 ↓→ Data Output Float Delay Time
–
*1: These symbols are the corresponding µPD27C256 symbols.
2: The internal address signal is incremented by 1 at the fourth rising edge of X1 input. The internal
address is not connected to any pin.
26
µPD75P308
PROGRAM MEMORY WRITE TIMING
tVPS
VPP
VPP
VDD
tVDS
VDD+1
VDD
VDD
tXH
X1
tXL
P40-P43
P50-P53
Data
Data input
Data input
Data input
output
tDS
tDH
tAH
tI
tOH
tDV
tDF
tDS
tAS
MD0
MD1
tMOS
tPW
tM1R
tOPW
tPCR
tM1S
tM1H
MD2
MD3
tM3H
tM3S
PROGRAM MEMORY READ TIMING
tVPS
VPP
VDD
VPP
tVDS
VDD+1
VDD
VDD
tXH
X1
tXL
tDAD
tHAD
P40-P43
P50-P53
Data output
Data output
tDV
tDFR
t
I
tM3HR
MD0
MD1
MD2
tPCR
tM3SR
MD3
27
µPD75P308
5. PACKAGE DRAWINGS
80 PIN PLASTIC QFP (14×20)
A
B
41
40
64
65
detail of lead end
25
24
80
1
G
H
M
N
I
J
K
L
P80GF-80-3B9-2
NOTE
ITEM
MILLIMETERS
INCHES
Each lead centerline is located within 0.15
mm (0.006 inch) of its true position (T.P.) at
maximum material condition.
±
±
A
B
C
D
F
23.6 0.4
0.929 0.016
+0.009
±
20.0 0.2
0.795
–0.008
+0.009
±
14.0 0.2
0.551
–0.008
±
±
0.693 0.016
17.6 0.4
1.0
0.8
0.039
G
H
I
0.031
+0.004
±
0.35 0.10
0.014
–0.005
0.15
0.006
J
0.8 (T.P.)
0.031 (T.P.)
+0.008
±
K
L
1.8 0.2
0.071
–0.009
+0.009
±
0.031
0.8 0.2
–0.008
+0.10
+0.004
0.15
M
N
P
Q
S
0.006
–0.05
–0.003
0.15
2.7
0.006
0.106
±
±
0.1 0.1
0.004 0.004
3.0 MAX.
0.119 MAX.
28
µPD75P308
80 PIN CERAMIC WQFN
A
B
Q
K
T
80
1
M
I
H
U
J
R
X80KW-80A-1
NOTE
ITEM
A
MILLIMETERS
INCHES
Each lead centerline is located within 0.08
mm (0.003 inch) of its true position (T.P.) at
maximum material condition.
+0.017
±
20.0 0.4
0.787
–0.016
B
19.0
13.2
0.748
0.520
C
±
±
D
E
14.2 0.4
0.559 0.016
0.065
1.64
F
2.14
0.084
G
H
I
4.064 MAX.
0.160 MAX.
±
±
0.51 0.10
0.020 0.004
0.08
0.003
J
0.8 (T.P.)
0.031 (T.P.)
+0.009
±
K
1.0 0.2
0.039
–0.008
Q
R
C 0.5
0.8
C 0.020
0.031
S
1.1
0.043
T
R 3.0
12.0
R 0.118
U
W
0.472
+0.008
±
0.75 0.2
0.030
–0.009
29
µPD75P308
★
6. RECOMMENDED SOLDERING CONDITIONS
It is recommended that µPD75P308 be soldered under the following conditions.
For details on the recommended soldering conditions, refer to Information Document "Semiconductor
Devices Mounting Manual" (IEI-616).
The soldering methods and conditions are not listed here, consult NEC.
Table 6-1 Soldering Conditions
µPD75P308GF-3B9: 80-pin plastic QFP (14 x 20 mm)
Symbol for Recommended
Soldering Method
Wave Soldering
Soldering Conditions
Condition
Soldering bath temperature: 260°C max.,
time: 10 seconds max., number of times: 1,
pre-heating temperature: 120°C max. (package surface
temperature), maximum number of days: 2 days*,
(beyond this period, 16 hours of pre-baking is required
at 125°C).
WS60-162-1
Infrared Reflow
Package peak temperature: 230°C,
IR30-162-1
VP15-162-1
—
time: 30 seconds max. (210°C min.),
number of times: 1, maximum number of days: 2 days*
(beyond this period, 16 hours of pre-baking is required
at 125°C)
VPS
Package peak temperature: 215°C,
time: 40 seconds max. (200°C min.),
number of times: 1, maximum number of days: 2 days*
(beyond this period, 16 hours of pre-baking is required
at 125°C)
Pin Partial Heating
Pin temperature: 300°C max.,
time: 3 seconds max. (per side)
*: Number of days after unpacking the dry pack. Storage conditions are 25°C and 65%RH max.
Caution: Do not use two or more soldering methods in combination (except the pin partial heating
method).
Notice
A model that can be soldered under the more stringent conditions (infrared reflow peak
temperature: 235°C, number of times: 2, and an extended number of days) is also available.
For details, consult NEC.
30
µPD75P308
APPENDIX A. DEVELOPMENT TOOLS
The following development support tools are readily available to support development of systems using
µPD75P308:
PROM writing tools
Hardare
IE-75000-R*1
In-circuit emulator for 75K series
IE-75001-R
IE-75000-R-EM*2
Emulation board for IE-75000-R and IE-75001-R
EP-75308GF-R
Emulation prove for µPD75P308GF, provided with 80-pin conversion socket,
EV-9200G-80
EV-9200G-80.
PG-1500
PROM programmer
PA-75P308GF
PROM programmer adapter solely used for µPD75P308GF. It is connected to
PG-1500.
PA-75P308K
PROM programmer adapter solely used for µPD75P308K. It is connected to
PG-1500.
Software
IE Control Program
PG-1500 Controller
RA75X Relocatable
Assembler
Host machine
•
•
PC-9800 series (MS-DOSTM Ver.3.30 to Ver.5.00A*3)
IBM PC/ATTM (PC DOSTM Ver.3.1)
*1: Maintenance product
2: Not provided with IE-75001-R
3: Ver.5.00/5.00A has a task swap function, but this function cannot be used with this software.
Remarks: For development tools from other companies, refer to 75X Series Selection Guide (IF-151).
31
µPD75P308
★
APPENDIX B. RELATED DOCUMENTS
32
µPD75P308
GENERAL NOTES ON CMOS DEVICES
1
STATIC ELECTRICITY (ALL MOS DEVICES)
Exercise care so that MOS devices are not adversely influenced by static electricity while being
handled.
The insulation of the gates of the MOS device may be destroyed by a strong static charge.
Therefore, when transporting or storing the MOS device, use a conductive tray, magazine case,
or conductive buffer materials, or the metal case NEC uses for packaging and shipment, and use
grounding when assembling the MOS device system. Do not leave the MOS device on a plastic
plate and do not touch the pins of the device.
Handle boards on which MOS devices are mounted similarly .
2
PROCESSING OF UNUSED PINS (CMOS DEVICES ONLY)
Fix the input level of CMOS devices.
Unlike bipolar or NMOS devices, if a CMOS device is operated with nothing connected to its
input pin, intermediate level input may be generated due to noise, and an inrush current may flow
through the device, causing the device to malfunction. Therefore, fix the input level of the device
by using a pull-down or pull-up resistor. If there is a possibility that an unused pin serves as an
output pin (whose timing is not specified), each pin should be connected to VDD or GND through
a resistor.
Refer to “Processing of Unused Pins” in the documents of each devices.
3
STATUS BEFORE INITIALIZATION (ALL MOS DEVICES)
The initial status of MOS devices is undefined upon power application.
Since the characteristics of an MOS device are determined by the quantity of injection at the
molecular level, the initial status of the device is not controlled during the production process. The
output status of pins, I/O setting, and register contents upon power application are not guaranteed.
However, the items defined for reset operation and mode setting are subject to guarantee after
the respective operations have been executed.
When using a device with a reset function, be sure to reset the device after power application.
33
µPD75P308
[MEMO]
No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which
may appear in this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other
intellectual property rights of third parties by or arising from use of a device described herein or any other
liability arising from use of such device. No license, either express, implied or otherwise, is granted
under any patents, copyrights or other intellectual property rights of NEC Corporation or others.
The devices listed in this document are not suitable for uses in aerospace equipment, submarine cables,
nuclear reactor control systems and life support systems. If customers intend to use NEC devices for
above applications or they intend to use "Standard" quality grade NEC devices for the applications not
intended by NEC, please contact our sales people in advance.
Application examples recommended by NEC Corporation
Standard: Computer, Officeequipment, Communicationequipment, TestandMeasurementequipment,
Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products,etc.
Special: Automotive and Transportation equipment, Traffic control systems, Antidisaster systems,
Anticrime system, etc.
M4 92.6
MS-DOS is a trademark of Microsoft Corporation.
PC DOS and PC/AT are trademarks of IBM Corporation.
|