Atmel Computer Hardware ATmega324PA User Manual

Features

• High-performance, Low-power AVR^®8-bit Microcontroller

• Advanced RISC Architecture

– 131 Powerful Instructions – Most Single-clock Cycle Execution

– 32 x 8 General Purpose Working Registers

– Fully Static Operation

– Up to 20 MIPS Throughput at 20 MHz

– On-chip 2-cycle Multiplier

• High Endurance Non-volatile Memory segments

– 32K Bytes of In-System Self-programmable Flash program memory

– 1K Bytes EEPROM

8-bit

– 2K Bytes Internal SRAM

– Write/Erase Cycles: 10,000 Flash/ 100,000 EEPROM

– Data retention: 20 years at 85°C/ 100 years at 25°C⁽¹⁾

– Optional Boot Code Section with Independent Lock Bits

In-System Programming by On-chip Boot Program

True Read-While-Write Operation

Microcontroller

with 32K Bytes

In-System

Programmable

Flash

– Programming Lock for Software Security

• JTAG (IEEE std. 1149.1 Compliant) Interface

– Boundary-scan Capabilities According to the JTAG Standard

– Extensive On-chip Debug Support

– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface

• Peripheral Features

– Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes

– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode

– Real Time Counter with Separate Oscillator

– Six PWM Channels

ATmega324PA

– 8-channel, 10-bit ADC

Differential mode with selectable gain at 1x, 10x or 200x

– Byte-oriented Two-wire Serial Interface

– Two Programmable Serial USART

– Master/Slave SPI Serial Interface

– Programmable Watchdog Timer with Separate On-chip Oscillator

– On-chip Analog Comparator

– Interrupt and Wake-up on Pin Change

Summary

• Special Microcontroller Features

– Power-on Reset and Programmable Brown-out Detection

– Internal Calibrated RC Oscillator

– External and Internal Interrupt Sources

– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby and

Extended Standby

• I/O and Packages

– 32 Programmable I/O Lines

– 40-pin PDIP, 44-lead TQFP, 44-pad VQFN/QFN/MLF

– 44-pad DRQFN

– 49-ball VFBGA

• Operating Voltages

– 1.8 - 5.5V

• Speed Grades

– 0 - 20MHz @ 1.8 - 5.5V

• Power Consumption at 1 MHz, 1.8V, 25°C

– Active: 0.4 mA

– Power-down Mode: 0.1µA

– Power-save Mode: 0.6µA (Including 32 kHz RTC)

8152AS–AVR–11/08

ATmega324PA

1.2

Pinout - DRQFN

Figure 1-2. DRQFN - Pinout

Top view

Bottom view

A18

B15

A17

B14

A16

B13

A15

B12

A14

B11

A13

A18

B15

A17

B14

A16

B13

A15

B12

A14

B11

A13

Table 1-1.

DRQFN - Pinout

PB5

PB6

PD3

PD4

PD5

PD6

PD7

VCC

GND

PC0

PC1

PC2

PC3

A13

B11

A14

B12

A15

B13

A16

B14

A17

B15

A18

PC4

PC5

PC6

PC7

AVCC

GND

AREF

PA7

A19

B16

A20

B17

A21

B18

A22

B19

A23

B20

A24

PA3

PA2

PA1

PA0

VCC

GND

PB0

PB1

PB2

PB3

PB4

PB7

RESET

VCC

GND

XTAL2

XTAL1

PD0

A10

A11

B10

A12

PA6

PD1

PA5

PD2

PA4

8152AS–AVR–11/08

1.3

Pinout - VFBGA

Figure 1-3. VFBGA - Pinout

Top view

Bottom view

Table 1-2.

BGA - Pinout

GND

PB6

PB4

PB5

PB2

PB3

PB7

PD0

PD5

PD6

VCC

GND

PB0

PB1

GND

PD7

PC0

GND

VCC

PA0

PA1

PA4

PC5

PC2

PC1

PA2

PA3

PA6

PA7

PC7

PC4

PC3

GND

PA5

VCC

GND

XTAL1

PD2

RESET

XTAL2

PD1

AREF

GND

AVCC

PC6

PD3

GND

PD4

GND

ATmega324PA

8152AS–AVR–11/08

ATmega324PA

2. Overview

The ATmega324PA is a low-power CMOS 8-bit microcontroller based on the AVR enhanced

RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega324PA

achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize

power consumption versus processing speed.

2.1

Block Diagram

Figure 2-1. Block Diagram

PA7..0

PB7..0

VCC

Power

Supervision

POR / BOD &

RESET

PORT A (8)

PORT B (8)

RESET

Watchdog

Timer

GND

Analog

Comparator

A/D

Converter

Watchdog

Oscillator

USART 0

XTAL1

Oscillator

Circuits /

Clock

Internal

Bandgap reference

EEPROM

SPI

Generation

XTAL2

8bit T/C 0

CPU

JTAG/OCD

TWI

16bit T/C 1

8bit T/C 2

USART 1

FLASH

SRAM

PORT C (8)

PORT D (8)

PD7..0

TOSC2/PC7 TOSC1/PC6

PC5..0

The AVR core combines a rich instruction set with 32 general purpose working registers. All the

32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent

registers to be accessed in one single instruction executed in one clock cycle. The resulting

architecture is more code efficient while achieving throughputs up to ten times faster than con-

ventional CISC microcontrollers.

8152AS–AVR–11/08

The ATmega324PA provides the following features: 32K bytes of In-System Programmable

Flash with Read-While-Write capabilities, 1K bytes EEPROM, 2K bytes SRAM, 32 general pur-

pose I/O lines, 32 general purpose working registers, Real Time Counter (RTC), three flexible

Timer/Counters with compare modes and PWM, 2 USARTs, a byte oriented 2-wire Serial Inter-

face, a 8-channel, 10-bit ADC with optional differential input stage with programmable gain,

programmable Watchdog Timer with Internal Oscillator, an SPI serial port, IEEE std. 1149.1

compliant JTAG test interface, also used for accessing the On-chip Debug system and program-

ming and six software selectable power saving modes. The Idle mode stops the CPU while

allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The

Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip

functions until the next interrupt or Hardware Reset. In Power-save mode, the asynchronous

timer continues to run, allowing the user to maintain a timer base while the rest of the device is

sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except Asynchro-

nous Timer and ADC, to minimize switching noise during ADC conversions. In Standby mode,

the Crystal/Resonator Oscillator is running while the rest of the device is sleeping. This allows

very fast start-up combined with low power consumption. In Extended Standby mode, both the

main Oscillator and the Asynchronous Timer continue to run.

The device is manufactured using Atmel’s high-density nonvolatile memory technology. The On-

chip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial

interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program

running on the AVR core. The boot program can use any interface to download the application

program in the application Flash memory. Software in the Boot Flash section will continue to run

while the Application Flash section is updated, providing true Read-While-Write operation. By

combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip,

the Atmel ATmega324PA is a powerful microcontroller that provides a highly flexible and cost

effective solution to many embedded control applications.

The ATmega324PA AVR is supported with a full suite of program and system development tools

including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators,

and evaluation kits.

ATmega324PA

8152AS–AVR–11/08

ATmega324PA

2.2

Pin Descriptions

2.2.1

VCC

Digital supply voltage.

2.2.2

2.2.3

GND

Ground.

Port A (PA7:PA0)

Port A serves as analog inputs to the Analog-to-digital Converter.

Port A also serves as an 8-bit bi-directional I/O port with internal pull-up resistors (selected for

each bit). The Port A output buffers have symmetrical drive characteristics with both high sink

and source capability. As inputs, Port A pins that are externally pulled low will source current if

the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes

active, even if the clock is not running.

Port A also serves the functions of various special features of the ATmega324PA as listed on

page 81.

2.2.4

2.2.5

2.2.6

Port B (PB7:PB0)

Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port B output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port B also serves the functions of various special features of the ATmega324PA as listed on

page 83.

Port C (PC7:PC0)

Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port C output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port C pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port C also serves the functions of the JTAG interface, along with special features of the

ATmega324PA as listed on page 86.

Port D (PD7:PD0)

Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port D output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port D pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port D also serves the functions of various special features of the ATmega324PA as listed on

page 88.

8152AS–AVR–11/08

2.2.7

RESET

Reset input. A low level on this pin for longer than the minimum pulse length will generate a

reset, even if the clock is not running. The minimum pulse length is given in ”System and Reset

Characteristics” on page 329. Shorter pulses are not guaranteed to generate a reset.

2.2.8

2.2.9

2.2.10

XTAL1

XTAL2

AVCC

Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.

Output from the inverting Oscillator amplifier.

AVCC is the supply voltage pin for Port A and the Analog-to-digital Converter. It should be exter-

nally connected to V_CC, even if the ADC is not used. If the ADC is used, it should be connected

to V_CCthrough a low-pass filter.

2.2.11

AREF

This is the analog reference pin for the Analog-to-digital Converter.

3. Resources

A comprehensive set of development tools, application notes and datasheetsare available for

download on http://www.atmel.com/avr.

4. Data Retention

Reliability Qualification results show that the projected data retention failure rate is much less

than 1 PPM over 20 years at 85°C or 100 years at 25°C.

ATmega324PA

8152AS–AVR–11/08

ATmega324PA

5. Register Summary

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

(0xFF)

(0xFE)

(0xFD)

(0xFC)

(0xFB)

(0xFA)

(0xF9)

(0xF8)

(0xF7)

(0xF6)

(0xF5)

(0xF4)

(0xF3)

(0xF2)

(0xF1)

(0xF0)

(0xEF)

(0xEE)

(0xED)

(0xEC)

(0xEB)

(0xEA)

(0xE9)

(0xE8)

(0xE7)

(0xE6)

(0xE5)

(0xE4)

(0xE3)

(0xE2)

(0xE1)

(0xE0)

(0xDF)

(0xDE)

(0xDD)

(0xDC)

(0xDB)

(0xDA)

(0xD9)

(0xD8)

(0xD7)

(0xD6)

(0xD5)

(0xD4)

(0xD3)

(0xD2)

(0xD1)

(0xD0)

(0xCF)

(0xCE)

(0xCD)

(0xCC)

(0xCB)

(0xCA)

(0xC9)

(0xC8)

(0xC7)

(0xC6)

(0xC5)

(0xC4)

(0xC3)

(0xC2)

(0xC1)

Reserved

UDR1

USART1 I/O Data Register

190

UBRR1H

UBRR1L

Reserved

UCSR1C

UCSR1B

UCSR1A

Reserved

UDR0

USART1 Baud Rate Register High Byte

194/207

USART1 Baud Rate Register Low Byte

UMSEL10

TXCIE1

TXC1

UMSEL11

RXCIE1

RXC1

RXEN1

FE1

UDORD1

UCSZ12

UPE1

UCPHA1

RXB81

U2X1

UCPOL1

TXB81

MPCM1

192/206

191/205

190/205

UDRIE1

UDRE1

TXEN1

DOR1

USART0 I/O Data Register

190

UBRR0H

UBRR0L

Reserved

UCSR0C

UCSR0B

USART0 Baud Rate Register High Byte

194/207

USART0 Baud Rate Register Low Byte

UMSEL01

RXCIE0

UMSEL00

TXCIE0

UDORD0

UCSZ02

UCPHA0

RXB80

UCPOL0

TXB80

192/206

191/205

UDRIE0

RXEN0

TXEN0

8152AS–AVR–11/08

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

(0xC0)

(0xBF)

(0xBE)

(0xBD)

(0xBC)

(0xBB)

(0xBA)

(0xB9)

(0xB8)

(0xB7)

(0xB6)

(0xB5)

(0xB4)

(0xB3)

(0xB2)

(0xB1)

(0xB0)

(0xAF)

(0xAE)

(0xAD)

(0xAC)

(0xAB)

(0xAA)

(0xA9)

(0xA8)

(0xA7)

(0xA6)

(0xA5)

(0xA4)

(0xA3)

(0xA2)

(0xA1)

(0xA0)

(0x9F)

(0x9E)

(0x9D)

(0x9C)

(0x9B)

(0x9A)

(0x99)

(0x98)

(0x97)

(0x96)

(0x95)

(0x94)

(0x93)

(0x92)

(0x91)

(0x90)

(0x8F)

(0x8E)

(0x8D)

(0x8C)

(0x8B)

(0x8A)

(0x89)

(0x88)

(0x87)

(0x86)

(0x85)

(0x84)

(0x83)

(0x82)

(0x81)

(0x80)

(0x7F)

UCSR0A

Reserved

TWAMR

TWCR

RXC0

TXC0

UDRE0

FE0

DOR0

UPE0

U2X0

MPCM0

190/205

TWAM6

TWINT

TWAM5

TWEA

TWAM4

TWSTA

TWAM3

TWSTO

TWAM2

TWWC

TWAM1

TWEN

TWAM0

236

233

235

236

235

233

TWIE

TWDR

2-wire Serial Interface Data Register

TWAR

TWA6

TWS7

TWA5

TWS6

TWA4

TWS5

TWA3

TWS4

TWA2

TWS3

TWA1

TWA0

TWGCE

TWPS0

TWSR

TWPS1

TWBR

2-wire Serial Interface Bit Rate Register

Reserved

ASSR

AS2

EXCLK

TCN2UB

OCR2AUB

OCR2BUB

TCR2AUB

TCR2BUB

158

Reserved

OCR2B

Timer/Counter2 Output Compare Register B

Timer/Counter2 Output Compare Register A

Timer/Counter2 (8 Bit)

158

157

156

153

OCR2A

TCNT2

TCCR2B

TCCR2A

Reserved

OCR1BH

OCR1BL

OCR1AH

OCR1AL

ICR1H

FOC2A

FOC2B

WGM22

CS22

CS21

CS20

COM2A1

COM2A0

COM2B1

COM2B0

WGM21

WGM20

Timer/Counter1 - Output Compare Register B High Byte

Timer/Counter1 - Output Compare Register B Low Byte

Timer/Counter1 - Output Compare Register A High Byte

Timer/Counter1 - Output Compare Register A Low Byte

Timer/Counter1 - Input Capture Register High Byte

Timer/Counter1 - Input Capture Register Low Byte

Timer/Counter1 - Counter Register High Byte

137

138

137

ICR1L

TCNT1H

TCNT1L

Reserved

TCCR1C

TCCR1B

TCCR1A

DIDR1

Timer/Counter1 - Counter Register Low Byte

FOC1A

ICNC1

COM1A1

FOC1B

ICES1

COM1A0

136

135

133

240

WGM13

COM1B0

WGM12

CS12

CS11

WGM11

AIN1D

CS10

WGM10

AIN0D

COM1B1

ATmega324PA

8152AS–AVR–11/08

ATmega324PA

Address

Name

DIDR0

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

(0x7E)

(0x7D)

ADC7D

ADC6D

ADC5D

ADC4D

ADC3D

ADC2D

ADC1D

ADC0D

260

Reserved

ADMUX

ADCSRB

ADCSRA

ADCH

(0x7C)

REFS1

REFS0

ACME

ADSC

ADLAR

MUX4

MUX3

MUX2

ADTS2

ADPS2

MUX1

ADTS1

ADPS1

MUX0

ADTS0

ADPS0

256

239

258

259

(0x7B)

(0x7A)

ADEN

ADATE

ADIF

ADIE

(0x79)

ADC Data Register High byte

ADC Data Register Low byte

(0x78)

ADCL

(0x77)

Reserved

PCMSK3

Reserved

TIMSK2

TIMSK1

TIMSK0

PCMSK2

PCMSK1

PCMSK0

Reserved

EICRA

(0x76)

(0x75)

(0x74)

(0x73)

PCINT31

PCINT30

PCINT29

PCINT28

PCINT27

PCINT26

PCINT25

PCINT24

(0x72)

(0x71)

(0x70)

OCIE2B

OCIE1B

OCIE0B

PCINT18

PCINT10

PCINT2

OCIE2A

OCIE1A

OCIE0A

PCINT17

PCINT9

PCINT1

TOIE2

TOIE1

TOIE0

PCINT16

PCINT8

PCINT0

159

138

110

(0x6F)

ICIE1

(0x6E)

(0x6D)

PCINT23

PCINT22

PCINT21

PCINT20

PCINT19

PCINT11

PCINT3

(0x6C)

PCINT15

PCINT14

PCINT13

PCINT12

(0x6B)

PCINT7

PCINT6

PCINT5

PCINT4

(0x6A)

(0x69)

ISC21

ISC20

ISC11

PCIE3

ISC10

PCIE2

ISC01

PCIE1

ISC00

PCIE0

(0x68)

PCICR

(0x67)

Reserved

OSCCAL

Reserved

PRR

(0x66)

Oscillator Calibration Register

(0x65)

(0x64)

PRTWI

PRTIM2

PRTIM0

PRUSART1

PRTIM1

PRSPI

PRUSART0

PRADC

(0x63)

Reserved

CLKPR

WDTCSR

SREG

(0x62)

(0x61)

CLKPCE

CLKPS3

CLKPS2

CLKPS1

CLKPS0

(0x60)

WDIF

WDIE

WDP3

WDCE

WDE

WDP2

WDP1

WDP0

0x3F (0x5F)

0x3E (0x5E)

0x3D (0x5D)

0x3C (0x5C)

0x3B (0x5B)

0x3A (0x5A)

0x39 (0x59)

0x38 (0x58)

0x37 (0x57)

0x36 (0x56)

0x35 (0x55)

0x34 (0x54)

0x33 (0x53)

0x32 (0x52)

0x31 (0x51)

0x30 (0x50)

0x2F (0x4F)

0x2E (0x4E)

0x2D (0x4D)

0x2C (0x4C)

0x2B (0x4B)

0x2A (0x4A)

0x29 (0x49)

0x28 (0x48)

0x27 (0x47)

0x26 (0x46)

0x25 (0x45)

0x24 (0x44)

0x23 (0x43)

0x22 (0x42)

0x21 (0x41)

0x20 (0x40)

0x1F (0x3F)

0x1E (0x3E)

0x1D (0x3D)

SPH

SP15

SP14

SP13

SP12

SP11

SP10

SP9

SP8

SPL

SP7

SP6

SP5

SP4

SP3

SP2

SP1

SP0

Reserved

RAMPZ

Reserved

SPMCSR

Reserved

MCUCR

MCUSR

SMCR

RAMPZ0

PGERS

SPMEN

SPMIE

RWWSB

SIGRD

RWWSRE

BLBSET

PGWRT

290

JTD

BODS

BODSE

PUD

WDRF

SM2

BORF

SM1

IVSEL

EXTRF

SM0

IVCE

PORF

92/276

59/276

JTRF

Reserved

OCDR

On-Chip Debug Register

266

258

ACSR

ACD

ACBG

ACO

ACI

ACIE

ACIC

ACIS1

ACIS0

Reserved

SPDR

SPI 0 Data Register

171

170

169

SPSR

SPIF0

SPIE0

WCOL0

SPE0

SPI2X0

SPR00

SPCR

DORD0

MSTR0

CPOL0

CPHA0

SPR01

GPIOR2

GPIOR1

Reserved

OCR0B

OCR0A

TCNT0

General Purpose I/O Register 2

General Purpose I/O Register 1

Timer/Counter0 Output Compare Register B

Timer/Counter0 Output Compare Register A

Timer/Counter0 (8 Bit)

110

109

108

110

160

TCCR0B

TCCR0A

GTCCR

EEARH

EEARL

FOC0A

COM0A1

TSM

FOC0B

WGM02

CS02

CS01

CS00

COM0A0

COM0B1

COM0B0

WGM01

PSRASY

WGM00

PSR5SYNC

EEPROM Address Register High Byte

EEPROM Address Register Low Byte

EEPROM Data Register

EEDR

EECR

EEPM1

EEPM0

EERIE

EEMPE

INT2

EEPE

INT1

EERE

INT0

GPIOR0

EIMSK

General Purpose I/O Register 0

8152AS–AVR–11/08

Address

Name

EIFR

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

0x1C (0x3C)

0x1B (0x3B)

0x1A (0x3A)

0x19 (0x39)

0x18 (0x38)

0x17 (0x37)

0x16 (0x36)

0x15 (0x35)

0x14 (0x34)

0x13 (0x33)

0x12 (0x32)

0x11 (0x31)

0x10 (0x30)

0x0F (0x2F)

0x0E (0x2E)

0x0D (0x2D)

0x0C (0x2C)

0x0B (0x2B)

0x0A (0x2A)

0x09 (0x29)

0x08 (0x28)

0x07 (0x27)

0x06 (0x26)

0x05 (0x25)

0x04 (0x24)

0x03 (0x23)

0x02 (0x22)

0x01 (0x21)

0x00 (0x20)

INTF2

INTF1

INTF0

PCIFR

PCIF3

PCIF2

PCIF1

PCIF0

Reserved

TIFR2

OCF2B

OCF2A

TOV2

160

139

110

TIFR1

ICF1

OCF1B

OCF1A

TOV1

TIFR0

OCF0B

OCF0A

TOV0

Reserved

PORTD

DDRD

PORTD7

DDD7

PIND7

PORTC7

DDC7

PINC7

PORTB7

DDB7

PINB7

PORTA7

DDA7

PINA7

PORTD6

DDD6

PIND6

PORTC6

DDC6

PINC6

PORTB6

DDB6

PINB6

PORTA6

DDA6

PINA6

PORTD5

DDD5

PIND5

PORTC5

DDC5

PINC5

PORTB5

DDB5

PINB5

PORTA5

DDA5

PINA5

PORTD4

DDD4

PIND4

PORTC4

DDC4

PINC4

PORTB4

DDB4

PINB4

PORTA4

DDA4

PINA4

PORTD3

DDD3

PIND3

PORTC3

DDC3

PINC3

PORTB3

DDB3

PINB3

PORTA3

DDA3

PINA3

PORTD2

DDD2

PIND2

PORTC2

DDC2

PINC2

PORTB2

DDB2

PINB2

PORTA2

DDA2

PINA2

PORTD1

DDD1

PIND1

PORTC1

DDC1

PINC1

PORTB1

DDB1

PINB1

PORTA1

DDA1

PINA1

PORTD0

DDD0

PIND0

PORTC0

DDC0

PINC0

PORTB0

DDB0

PINB0

PORTA0

DDA0

PINA0

PIND

PORTC

DDRC

PINC

PORTB

DDRB

PINB

PORTA

DDRA

PINA

Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses

should never be written.

2. I/O registers within the address range $00 - $1F are directly bit-accessible using the SBI and CBI instructions. In these reg-

isters, the value of single bits can be checked by using the SBIS and SBIC instructions.

3. Some of the status flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on

all bits in the I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions

work with registers 0x00 to 0x1F only.

4. When using the I/O specific commands IN and OUT, the I/O addresses $00 - $3F must be used. When addressing I/O regis-

ters as data space using LD and ST instructions, $20 must be added to these addresses. The ATmega324PA is a complex

microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and

OUT instructions. For the Extended I/O space from $60 - $FF, only the ST/STS/STD and LD/LDS/LDD instructions can be

used.

ATmega324PA

8152AS–AVR–11/08

ATmega324PA

6. Instruction Set Summary

Mnemonics

Operands

Description

Operation

Flags

#Clocks

ARITHMETIC AND LOGIC INSTRUCTIONS

ADD

Rd, Rr

Rdl,K

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rdl,K

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rd, Rr

Add two Registers

Rd ← Rd + Rr

Z,C,N,V,H

Z,C,N,V,S

Z,C,N,V,H

Z,C,N,V,S

Z,N,V

ADC

Add with Carry two Registers

Add Immediate to Word

Subtract two Registers

Subtract Constant from Register

Subtract with Carry two Registers

Subtract with Carry Constant from Reg.

Subtract Immediate from Word

Logical AND Registers

Logical AND Register and Constant

Logical OR Registers

Rd ← Rd + Rr + C

Rdh:Rdl ← Rdh:Rdl + K

Rd ← Rd - Rr

ADIW

SUB

SUBI

SBC

Rd ← Rd - K

Rd ← Rd - Rr - C

Rd ← Rd - K - C

Rdh:Rdl ← Rdh:Rdl - K

Rd ← Rd • Rr

SBCI

SBIW

AND

ANDI

Rd ← Rd • K

Z,N,V

Rd ← Rd v Rr

Z,N,V

ORI

Logical OR Register and Constant

Exclusive OR Registers

One’s Complement

Rd ← Rd v K

Z,N,V

EOR

COM

NEG

SBR

Rd ← Rd ⊕ Rr

Z,N,V

Rd ← 0xFF − Rd

Rd ← 0x00 − Rd

Rd ← Rd v K

Z,C,N,V

Z,C,N,V,H

Z,N,V

Two’s Complement

Rd,K

Set Bit(s) in Register

CBR

Clear Bit(s) in Register

Increment

Rd ← Rd • (0xFF - K)

Rd ← Rd + 1

Z,N,V

INC

Z,N,V

DEC

Decrement

Rd ← Rd − 1

Z,N,V

TST

Test for Zero or Minus

Clear Register

Rd ← Rd • Rd

Z,N,V

CLR

Rd ← Rd ⊕ Rd

Rd ← 0xFF

Z,N,V

SER

Set Register

None

MUL

Rd, Rr

Multiply Unsigned

R1:R0 ← Rd x Rr

^{R1:R0 ← (Rd x Rr)}<< 1

R1:R0 ← (Rd x Rr) << 1

Z,C

MULS

MULSU

FMUL

FMULS

FMULSU

Multiply Signed

Z,C

Multiply Signed with Unsigned

Fractional Multiply Unsigned

Fractional Multiply Signed

Fractional Multiply Signed with Unsigned

Z,C

BRANCH INSTRUCTIONS

RJMP

IJMP

Relative Jump

PC ← PC + k + 1

None

Indirect Jump to (Z)

PC ← Z

JMP

Direct Jump

PC ← k

RCALL

ICALL

CALL

RET

Relative Subroutine Call

Indirect Call to (Z)

PC ← PC + k + 1

PC ← Z

Direct Subroutine Call

Subroutine Return

PC ← k

PC ← STACK

RETI

Interrupt Return

PC ← STACK

CPSE

Rd,Rr

Compare, Skip if Equal

Compare

if (Rd = Rr) PC ← PC + 2 or 3

Rd − Rr

None

Z, N,V,C,H

None

1/2/3

Rd,Rr

CPC

Rd,Rr

Compare with Carry

Rd − Rr − C

CPI

Rd,K

Compare Register with Immediate

Skip if Bit in Register Cleared

Skip if Bit in Register is Set

Skip if Bit in I/O Register Cleared

Skip if Bit in I/O Register is Set

Branch if Status Flag Set

Branch if Status Flag Cleared

Branch if Equal

Rd − K

SBRC

SBRS

SBIC

SBIS

Rr, b

if (Rr(b)=0) PC ← PC + 2 or 3

if (Rr(b)=1) PC ← PC + 2 or 3

if (P(b)=0) PC ← PC + 2 or 3

if (P(b)=1) PC ← PC + 2 or 3

if (SREG(s) = 1) then PC←PC+k + 1

if (SREG(s) = 0) then PC←PC+k + 1

if (Z = 1) then PC ← PC + k + 1

if (Z = 0) then PC ← PC + k + 1

if (C = 1) then PC ← PC + k + 1

if (C = 0) then PC ← PC + k + 1

if (C = 1) then PC ← PC + k + 1

if (N = 1) then PC ← PC + k + 1

if (N = 0) then PC ← PC + k + 1

if (N ⊕ V= 0) then PC ← PC + k + 1

if (N ⊕ V= 1) then PC ← PC + k + 1

if (H = 1) then PC ← PC + k + 1

if (H = 0) then PC ← PC + k + 1

if (T = 1) then PC ← PC + k + 1

if (T = 0) then PC ← PC + k + 1

if (V = 1) then PC ← PC + k + 1

1/2/3

1/2

Rr, b

P, b

s, k

BRBS

BRBC

BREQ

BRNE

BRCS

BRCC

BRSH

BRLO

BRMI

BRPL

BRGE

BRLT

BRHS

BRHC

BRTS

BRTC

BRVS

Branch if Not Equal

Branch if Carry Set

Branch if Carry Cleared

Branch if Same or Higher

Branch if Lower

Branch if Minus

Branch if Plus

Branch if Greater or Equal, Signed

Branch if Less Than Zero, Signed

Branch if Half Carry Flag Set

Branch if Half Carry Flag Cleared

Branch if T Flag Set

Branch if T Flag Cleared

Branch if Overflow Flag is Set

8152AS–AVR–11/08

Mnemonics

Operands

Description

Operation

Flags

#Clocks

BRVC

BRIE

BRID

Branch if Overflow Flag is Cleared

if (V = 0) then PC ← PC + k + 1

if ( I = 1) then PC ← PC + k + 1

if ( I = 0) then PC ← PC + k + 1

None

1/2

Branch if Interrupt Enabled

Branch if Interrupt Disabled

None

BIT AND BIT-TEST INSTRUCTIONS

SBI

P,b

Set Bit in I/O Register

Clear Bit in I/O Register

Logical Shift Left

I/O(P,b) ← 1

None

CBI

I/O(P,b) ← 0

None

LSL

Rd(n+1) ← Rd(n), Rd(0) ← 0

Z,C,N,V

LSR

ROL

ROR

ASR

SWAP

BSET

BCLR

BST

BLD

SEC

CLC

SEN

CLN

SEZ

CLZ

SEI

Logical Shift Right

Rd(n) ← Rd(n+1), Rd(7) ← 0

Z,C,N,V

Rotate Left Through Carry

Rotate Right Through Carry

Arithmetic Shift Right

Swap Nibbles

Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7)

Z,C,N,V

Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0)

Z,C,N,V

Rd(n) ← Rd(n+1), n=0..6

Z,C,N,V

Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0)

None

Flag Set

SREG(s) ← 1

SREG(s) ← 0

T ← Rr(b)

Rd(b) ← T

C ← 1

SREG(s)

Flag Clear

SREG(s)

Rr, b

Rd, b

Bit Store from Register to T

Bit load from T to Register

Set Carry

None

Clear Carry

C ← 0

Set Negative Flag

N ← 1

Clear Negative Flag

Set Zero Flag

N ← 0

Z ← 1

Clear Zero Flag

Z ← 0

Global Interrupt Enable

Global Interrupt Disable

Set Signed Test Flag

Clear Signed Test Flag

Set Twos Complement Overflow.

Clear Twos Complement Overflow

Set T in SREG

I ← 1

CLI

I ← 0

SES

CLS

SEV

CLV

SET

CLT

SEH

CLH

S ← 1

S ← 0

V ← 1

V ← 0

T ← 1

Clear T in SREG

T ← 0

Set Half Carry Flag in SREG

Clear Half Carry Flag in SREG

H ← 1

H ← 0

DATA TRANSFER INSTRUCTIONS

MOV

MOVW

LDI

Rd, Rr

Rd, K

Move Between Registers

Copy Register Word

Rd ← Rr

None

Rd+1:Rd ← Rr+1:Rr

Load Immediate

Rd ← K

Rd, X

Load Indirect

Rd ← (X)

Rd, X+

Rd, - X

Rd, Y

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect

Rd ← (X), X ← X + 1

X ← X - 1, Rd ← (X)

Rd ← (Y)

Rd, Y+

Rd, - Y

Rd,Y+q

Rd, Z

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect with Displacement

Load Indirect

Rd ← (Y), Y ← Y + 1

Y ← Y - 1, Rd ← (Y)

Rd ← (Y + q)

LDD

Rd ← (Z)

Rd, Z+

Rd, -Z

Rd, Z+q

Rd, k

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect with Displacement

Load Direct from SRAM

Store Indirect

Rd ← (Z), Z ← Z+1

Z ← Z - 1, Rd ← (Z)

Rd ← (Z + q)

LDD

LDS

Rd ← (k)

X, Rr

(X) ← Rr

X+, Rr

- X, Rr

Y, Rr

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect

(X) ← Rr, X ← X + 1

X ← X - 1, (X) ← Rr

(Y) ← Rr

Y+, Rr

- Y, Rr

Y+q,Rr

Z, Rr

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect with Displacement

Store Indirect

(Y) ← Rr, Y ← Y + 1

Y ← Y - 1, (Y) ← Rr

(Y + q) ← Rr

STD

(Z) ← Rr

Z+, Rr

-Z, Rr

Z+q,Rr

k, Rr

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect with Displacement

Store Direct to SRAM

(Z) ← Rr, Z ← Z + 1

Z ← Z - 1, (Z) ← Rr

(Z + q) ← Rr

STD

STS

LPM

ELPM

(k) ← Rr

Load Program Memory

Load Program Memory and Post-Inc

Extended Load Program Memory

R0 ← (Z)

Rd, Z

Rd ← (Z)

Rd, Z+

Rd ← (Z), Z ← Z+1

R0 ← (RAMPZ:Z)

Rd ← (Z)

Rd, Z

Rd, Z+

Rd ← (RAMPZ:Z), RAMPZ:Z ←RAMPZ:Z+1

ATmega324PA

8152AS–AVR–11/08

ATmega324PA

Mnemonics

Operands

Description

Operation

Flags

#Clocks

SPM

Store Program Memory

In Port

(Z) ← R1:R0

Rd ← P

None

Rd, P

None

OUT

PUSH

POP

P, Rr

Out Port

P ← Rr

Push Register on Stack

Pop Register from Stack

STACK ← Rr

Rd ← STACK

MCU CONTROL INSTRUCTIONS

NOP

No Operation

Sleep

None

SLEEP

WDR

(see specific descr. for Sleep function)

(see specific descr. for WDR/timer)

For On-chip Debug Only

Watchdog Reset

Break

BREAK

N/A

8152AS–AVR–11/08

7. Ordering Information

7.1

ATmega324PA

Speed (MHz)⁽³⁾

Power Supply

Ordering Code⁽²⁾

Package⁽¹⁾

Operational Range

ATmega324PA-AU

ATmega324PA-PU

ATmega324PA-MU

ATmega324PA-MCH⁽⁴⁾

ATmega324PA-CU

44A

40P6

44M1

44MC

49C2

Industrial

1.8 - 5.5V

(-40^oC to 85^oC)

Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information

and minimum quantities.

2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also

Halide free and fully Green.

3. For Speed vs. V_CCsee ”Speed Grades” on page 327.

4. NiPdAu Lead Finish.

Package Type

44A

44-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP)

40P6

44M1

44MC

49C2

40-pin, 0.600” Wide, Plastic Dual Inline Package (PDIP)

44-pad, 7 x 7 x 1.0 mm body, lead pitch 0.50 mm, Thermally Enhanced Plastic Very Thin Quad Flat No-Lead (VQFN)

44-lead (2-row Staggered), 5 x 5 x 1.0 mm body, 2.60 x 2.60 mm Exposed Pad, Quad Flat No-Lead Package (QFN)

49-ball, (7 x 7 Array) 0.65 mm Pitch, 5 x 5 x 1 mm, Very Thin, Fine-Pitch Ball Grid Array Package (VFBGA)

ATmega324PA

8152AS–AVR–11/08

ATmega324PA

8. Packaging Information

8.1

44A

PIN 1

PIN 1 IDENTIFIER

0˚~7˚

COMMON DIMENSIONS

(Unit of Measure = mm)

MIN

–

MAX

1.20

NOM

NOTE

SYMBOL

–

0.05

0.95

11.75

9.90

11.75

9.90

0.30

0.09

0.45

0.15

1.00

12.00

10.00

12.00

10.00

–

1.05

12.25

10.10 Note 2

12.25

Notes:

1. This package conforms to JEDEC reference MS-026, Variation ACB.

2. Dimensions D1 and E1 do not include mold protrusion. Allowable

protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum

plastic body size dimensions including mold mismatch.

10.10 Note 2

0.45

–

0.20

3. Lead coplanarity is 0.10 mm maximum.

–

0.75

0.80 TYP

10/5/2001

TITLE

DRAWING NO. REV.

2325 Orchard Parkway

San Jose, CA 95131

44A, 44-lead, 10 x 10 mm Body Size, 1.0 mm Body Thickness,

0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)

44A

8152AS–AVR–11/08

8.2

40P6

SEATING PLANE

COMMON DIMENSIONS

(Unit of Measure = mm)

0º ~ 15º REF

MIN

–

MAX

4.826

–

NOM

NOTE

SYMBOL

–

0.381

52.070

15.240

13.462

0.356

1.041

3.048

0.203

15.494

–

52.578 Note 2

15.875

–

13.970 Note 2

0.559

–

1.651

Notes:

1. This package conforms to JEDEC reference MS-011, Variation AC.

2. Dimensions D and E1 do not include mold Flash or Protrusion.

Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").

–

3.556

–

0.381

17.526

2.540 TYP

09/28/01

DRAWING NO. REV.

40P6

TITLE

2325 Orchard Parkway

San Jose, CA 95131

40P6, 40-lead (0.600"/15.24 mm Wide) Plastic Dual

Inline Package (PDIP)

ATmega324PA

8152AS–AVR–11/08

ATmega324PA

8.3

44M1

Marked Pin# 1 ID

SEATING PLANE

TOP VIEW

Pin #1 Corner

SIDE VIEW

Pin #1

Triangle

Option A

COMMON DIMENSIONS

(Unit of Measure = mm)

MIN

0.80

–

MAX

1.00

0.05

NOM

0.90

NOTE

SYMBOL

Option B

Option C

0.02

Pin #1

Chamfer

(C 0.30)

0.20 REF

0.23

0.18

6.90

5.00

6.90

0.30

7.10

5.40

7.10

7.00

5.20

Pin #1

Notch

(0.20 R)

7.00

5.00

5.20

0.50 BSC

0.64

5.40

BOTTOM VIEW

0.59

0.20

0.69

0.41

Note: JEDEC Standard MO-220, Fig. 1 (SAW Singulation) VKKD-3.

0.26

9/26/08

GPC

ZWS

DRAWING NO.

TITLE

REV.

44M1, 44-pad, 7 x 7 x 1.0 mm Body, Lead

Pitch 0.50 mm, 5.20 mm Exposed Pad,Thermally

Enhanced Plastic Very Thin Quad Flat No

Lead Package (VQFN)

Package Drawing Contact:

packagedrawings@atmel.com

44M1

8152AS–AVR–11/08

8.4

44MC

Pin 1 ID

SIDE VIEW

TOP VIEW

eT/2

A19

A24

B20

B16

A18

COMMON DIMENSIONS

(Unit of Measure = mm)

B15

MIN

0.80

0.00

0.18

MAX

1.00

0.05

0.30

NOM

0.90

0.02

0.23

0.20 REF

5.00

2.60

5.00

2.60

0.70

0.40

–

NOTE

SYMBOL

0.40

R0.20

B11

4.90

2.55

4.90

2.55

–

5.10

2.65

5.10

2.65

–

A13

B10

A12

–

BOTTOM VIEW

0.45

0.30

0.00

–

0.35

–

0.40

0.075

1. The terminal #1 ID is a Laser-marked Feature.

Note:

9/13/07

DRAWING NO.

TITLE

REV.

44MC, 44QFN (2-Row Staggered), 5 x 5 x 1.00 mm Body,

2.60 x 2.60 mm Exposed Pad, Quad Flat No Lead Package

Package Drawing Contact:

packagedrawings@atmel.com

44MC

ATmega324PA

8152AS–AVR–11/08

ATmega324PA

8.5

49C2

A1 BALL ID

0.10

TOP VIEW

SIDE VIEW

COMMON DIMENSIONS

(Unit of Measure = mm)

MIN

–

MAX

1.00

–

NOM

–

NOTE

SYMBOL

0.20

0.65

4.90

–

A1 BALL CORNER

49 - Ø0.35 ± 0.05

–

5.00

5.10

BOTTOM VIEW

3.90 BSC

5.00

4.90

5.10

0.40

3.90 BSC

0.35

0.30

0.65 BSC

3/14/08

GPC

CBD

DRAWING NO.

TITLE

REV.

49C2, 49-ball (7 x 7 Array), 0.65 mm Pitch,

5.0 x 5.0 x 1.0 mm, Very Thin, Fine-Pitch

Ball Grid Array Package (VFBGA)

Package Drawing Contact:

packagedrawings@atmel.com

49C2

8152AS–AVR–11/08

9. Errata

9.1

ATmega324PA Rev. F

No known Errata.

ATmega324PA

8152AS–AVR–11/08

ATmega324PA

10. Datasheet Revision History

Please note that the referring page numbers in this section are referred to this document. The

referring revision in this section are referring to the document revision.

10.1 Rev. 8152A- 11/08

Initial revision (Based on the ATmega164P/324P/644P datasheet 8011K-AVR-09/08).

Changes done compared to ATmega164P/324P/644P datasheet 8011K-AVR-09/08:

– New graphics in ”Typical Characteristics” on page 336

– New ”Ordering Information” on page 16

8152AS–AVR–11/08

Headquarters

International

Atmel Corporation

2325 Orchard Parkway

San Jose, CA 95131

USA

Tel: 1(408) 441-0311

Fax: 1(408) 487-2600

Atmel Asia

Atmel Europe

Le Krebs

Atmel Japan

9F, Tonetsu Shinkawa Bldg.

1-24-8 Shinkawa

Chuo-ku, Tokyo 104-0033

Japan

Tel: (81) 3-3523-3551

Fax: (81) 3-3523-7581

Unit 1-5 & 16, 19/F

BEA Tower, Millennium City 5

418 Kwun Tong Road

Kwun Tong, Kowloon

Hong Kong

8, Rue Jean-Pierre Timbaud

BP 309

78054 Saint-Quentin-en-

Yvelines Cedex

France

Tel: (852) 2245-6100

Fax: (852) 2722-1369

Tel: (33) 1-30-60-70-00

Fax: (33) 1-30-60-71-11

Product Contact

Web Site

Technical Support

Sales Contact

www.atmel.com

[email protected]

www.atmel.com/contacts

Literature Requests

www.atmel.com/literature

Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any

intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI-

TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY

WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR

PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDEN-

TAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF

THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no

representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications

and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided

otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use

as components in applications intended to support or sustain life.

marks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others.

8152AS–AVR–11/08

Advantek Networks Network Card AWN 11N PCI User Manual
AEG Power Supply 1000 S User Manual
AKG Acoustics Video Game Headset C 544 L User Manual
Alpine Car Stereo System KD A815 User Manual
Aluratek Computer Drive AUHR200 User Manual
American DJ Indoor Furnishings Space Balls User Manual
Atlona Marine Radio AT HDWP RSNET User Manual
Axis Communications Security Camera P1204 User Manual
Axor Plumbing Product 06866000 User Manual
Badger Basket Safety Gate 1835 User Manual